2 edition of design of an asynchronous multiplier. found in the catalog.
design of an asynchronous multiplier.
Thesis (M.Sc.), - University of Manchester, Department of Computer Science.
|Contributions||University of Manchester. Department of Computer Science.|
|The Physical Object|
|Number of Pages||114|
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As for asynchronous multiplier,  minimizes power consumption of a multiplier by three methods such as asynchronous control, radix-2 algorithm, and split registers. The design in  is. A number of bundled-data asynchronous multiplier have been described that implement the modified Booth algorithm, in which the number of iterations is fixed – .
A bundled-data. With asynchronous circuit design becoming a powerful tool in the development of new digital systems, circuit designers are expected to have asynchronous design skills and be able to leverage them to reduce power consumption and increase system speed.
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